IC cards are known and, as a feature, carry an onboard semiconductor memory which can exchanged data with an external terminal. The word "terminal" is used in the generic sense to include any external device capable of exchanging data with the semiconductor memory of an IC card at addressed locations in that semiconductor memory.
Insofar as the present invention is concerned, the invention has broadest applicability to the type of IC card known as the memory card which does not include an onboard microprocessor. With non-microprocessor based memory cards, the external terminal is directly involved in generating addresses for the onboard IC card memory and for exchanging data with the addressed memory locations. However, as will become apparent to those skilled in this art upon reading of the following detailed description, in its broadest aspects the invention has applicability to microprocessor-based IC cards (sometimes called smart cards), particularly those where the external terminal has a significant function in determining where in the onboard memory particular items of data are to be stored.
IC cards and the associated external terminals have been configured with various bus structures compatible both with the processors in the terminals and the memory devices on the cards. For example, it is not unusual to have an IC card with a semiconductor memory on board which has an 8-bit data bus, and to configure the external terminal to exchange 8-bit data words with that memory. IC cards with 16-bit bus structures are also known, and 32-bit structures can be configured when the data storage requirements warrant that greater length of data word.
Use of IC cards has also progressed toward multiple-function cards where the same IC card is intended for use in a variety of external terminals. However, problems can arise when the bus structure of-the IC card is incompatible with the bus structure expected by the external terminal. Thus, it is common to limit the use of 8-bit data bus IC cards to 8-bit terminals, 16-bit cards to 16-bit terminals, and the like.
FIGS. 1 and 2 are block diagrams illustrating the internal structure without input/output, and certain control circuitry) of known 8-bit data bus and 16-bit data bus IC cards, respectively. It will be appreciated from an examination of these figures and from the following description that the cards are each particularly suited to function with 8-bit or 16-bit terminals, respectively, and that the cards are not interchangeable for use in terminals for which they are not designed.
Referring first to FIG. 1, there is shown an IC card especially configured for exchange of 8-bit data words. It is noted that FIG. 1 shows primarily the semiconductor memories and devices which control and interface with those memories in exchanging addressable data words with the external terminal. Additional interfacing circuitry, serial-to-parallel and parallel-to-serial converters, and the like are also utilized as is well known to those skilled in the art, but are not shown in the drawings. The drawings also omit circuitry for some of the control functions (such as read/write control) which are not necessary for an understanding of the present invention. Only the devices immediately associated with the memories and bus structure control are described herein in order to direct focus to the instant invention.
The IC card of FIG. 1 includes a pair of semiconductor memories 2, 3 which interface through a data bus buffer circuit 5 to an external data bus 6. The data bus 6 in turn couples 8-bit data words between the memory devices 2, 3 and the input/output circuitry of an external terminal (not shown). While data bus 6 is shown as a single line, it is illustrated by the slash mark shown thereacross that it is actually an 8-bit bus. For the purpose of addressing individual words within the memory devices 2, 3, an address bus generally indicated at 8 is provided for coupling address signals to the semiconductor memory and thereby addressing individual word locations in the memory. In the FIG. 1 embodiment, the address bus 8 is comprised of a high level or most significant address portion 9 (in the example only a single bit) and a low level or least significant address portion 10 (in the illustrated embodiment of 8 bits). It is seen that the low order address bus 10 is coupled to the address lines of both of the semiconductor memories 2, 3 for addressing individual words in those memories. The high order address signal is coupled to an address decoder circuit 1 which has a pair of outputs 12, 13 driving chip select lines CS1, CS2 of the respective memory devices 2, 3.
In operation, when the high order address on bus 9 is high, the outputs 12, 13 of the address decoder circuit 1 produce a low CS1 signal and a high CS2 signal. As a result, the semiconductor memory 2 is enabled while the semiconductor memory 3 is disabled, e.g., the data lines of the memory 3 are in a high impedance standby state. Thus, the semiconductor memory 2 will respond to the lower order bits on bus 10 and will allow the addressed word in the semiconductor memory 2 to be read or written under the control of additional control circuitry (not shown). Data which is written into or read out of the memory at the addressed location is coupled thereto via the data bus buffer circuit 5 via internal data bus 14.
It is seen that the internal data lines of the semiconductor memories (8-bits in each case in the example) which appear on internal data buses 14, 15 are connected in common and coupled to the same data bus buffer circuit 5. The semiconductor memory devices can have outputs in the form of tristate circuitry such that the internal data lines can be connected in common as illustrated and only the enabled memory (i.e, the memory enabled by the appropriate chip select signal) will control the state of the common data bus (in the read operation) or will be controlled by state of the common data bus (in the write operation).
It is also seen that the IC card of FIG. 1 includes a card enable signal coupled onto the card by means of signal line 11, and that the card enable signal is coupled both to the address decoder circuit 1 and the data bus buffer circuit 5. Thus, when the card enable signal CE is driven low (either by additional circuitry on the IC card or by means of a signal from the external terminal), the address decoder circuit 1 is enabled to respond to the high order bit on line 9, and the data bus buffer circuit 5 is enabled to couple signals between the external data bus 6 and the data lines 14, 15 of the semiconductor memory devices 2, 3.
By virtue of the selectability achieved by the high order address on line 9, the semiconductor memories 2, 3 are never enabled together, and operate separately and independently, even though they are driven by the same low order address bus. Whenever an address is coupled onto the address bus 8 which has a low signal in the high order bit on line 9, only the semiconductor memory device 3 will respond to the low order address bits to exchange data with the external data bus. In contrast, when the high order address on line 9 is high, only the semiconductor memory device 2 will respond to the low order address bits to exchange data with the external terminal. Since the data lines of both semiconductor devices are coupled in parallel through the same data bus buffer circuit, both of the devices read and write information into the same external data bus for coupling to the external terminal on that single 8-bit data bus.
FIG. 2 illustrates an IC card particularly configured for use in a system which requires a 16-bit data bus. As in the FIG. 1 embodiment, a pair of semiconductor memory devices 2, 3 are provided. However, in contrast to the prior embodiment, separate data bus buffer circuits 4, 5 are provided for driving separate sections 7a, 7b of an extended data bus 6. As in the prior embodiment, an 8-bit address bus 10 is coupled in parallel to both semiconductor memory devices 2, 3. However, there is no independent enablement of the memory devices 2, 3; instead, they are enabled together for writing into or reading out of in parallel, and the separate data bus buffer circuits 4, 5 for the respective memory devices 2, 3 facilitate that operation.
The card enable signal coupled to the card enable line 11 is shown to enable both semiconductor memory devices 2, 3 at the same time. In addition, that same signal enables data bus buffer circuits 4, 5 so that the data lines of the memories 2, 3 are coupled to respective portions 7a, 7b of the 16-bit data bus 6 to exchange 16-bit words with the external terminal. Thus, when the card is enabled and address signals are coupled to the memory devices via address bus 10, corresponding words are addressed in each of the memory circuits 2, 3. Since the external data bus is comprised of two sections 7a, 7b and each has its own data bus buffer circuit 5, 4, data on the respective bus sections is coupled to the individual data lines 14, 15 of the respective memory devices 2, 3 for writing into the memory devices in the write mode or reading out of the memory devices in the read mode. Thus, the memory devices 2, 3 are operated in parallel, and data words on the data lines 14, 15 are exchanged with a 16-bit external data bus 6 under control of signals on the address bus 10 in order to read out or write in 16-bit words in contrast to the 8-bit words utilized by the card of FIG. 1.
It will be appreciated that additional increments of bus structure can be provided, dependent upon the design requirements of the system, and the 8-bit and 16-bit systems of FIGS. 1 and 2 are merely exemplary. In some cases, 4-, 8- or 16-bit buses might be utilized, in other cases, 32-bit buses. It is typical, however, to configure the basic bus size to be of N bits, and bus sizes of ever-increasing complexity to be an integral number of N bits, most typically an integral number which is 2.sup.n, i.e., 2, 4, 8, etc.
It will also be appreciated, however, that even though there is such a relationship between relatively simple bus structures of few bits and more complex bus structures (more complex in that they can carry more information per addressed data word), there is no opportunity to utilize an IC card designed to operate with a given bus size in a terminal designed for a different bus configuration.